Modified Reed-Solomon multiplication

ABSTRACT

A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s 0  and s 1,  are computed for a sequence of data elements, using a selected primitive α that satisfies a selected primitive polynomial relation p(α)=0. Each of two checkbytes, c 0  and c 1,  is expressed as a linear combination of the syndromes s 0  and s 1,  where each coefficient of each linear combination is expressed as a single power of the primitive α and is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.

This application is related to a patent application, “REED-SOLOMONMULTIPLICATION METHOD”. U.S. Ser. No. 09/317,810, filed May 24, 1999,now U.S. Pat. No. 6,378,105.

FIELD OF THE INVENTION

This invention relates to use of error control techniques to detect andcorrect errors in a digital signal, and to efficient use of Reed-Solomonerror detection and correction.

BACKGROUND OF THE INVENTION

Approaches for error control encoding for computer communications havebeen proposed and used for more than 40 years. Error control is ofincreasing concern as the speed of digital signal transmission increasesby factors of ten each decade. Several error control schemes, such asthose developed by Reed-Solomon (RS) and by Bose-Chaudhuri-Hocquenhem(BCH), allow correction of “burst” errors of several consecutive bytesand are of special interest in computer communications. These errorcontrol schemes are powerful and allow detection and correction ofisolated bit errors and burst errors involving several consecutiveerroneous bits or bytes. However, the encoding and decoding proceduresare often long and complex, which limits digital signal throughput atthe transmitting end and/or at the receiving end where these errorcontrol methods are used. A Reed-Solomon error control proceduretypically requires matrix multiplication, or its equivalent, of largerow and/or column matrices as part of the syndrome processing. Thesemultiplications require a relatively large gate count in an HDL(hardware description language) formulation and add substantially to thetime required for such processing.

What is needed is an approach that allows reduction of the gate countfor pairwise multiplication in a Reed-Solomon error control procedureand decrease of the time required to form and to sum these pairwiseproducts. Preferably, the system should work with any reasonable codingblock dimensions and with any primitive polynomial used for Reed-Solomonencoding.

SUMMARY OF THE INVENTION

These needs are met by the invention, which provides a method forreducing the number of gates required and for decreasing the timerequired to form sums of products of pairs of elements, by using aparallel process to calculate the checkbyte(s) in an ECC processingphase for digital signals. The coefficients needed to form the sums ofproducts are built into and provided within the syndrome generator andcheckbyte generator modules so that these coefficients need not becomputed each time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (prior art) illustrates data flow within an ECC module.

FIG. 2 illustrates generation, storage and use of the syndromecomponents to form checkbyte components according to the invention.

FIG. 3 shows conventional apparatus for implementing certain sums andproducts.

FIGS. 4, 5 and 6 show apparatus for implementing Reed-Solomon multiplieraction according to the invention.

FIG. 7 is a flow chart illustrating practice according to the invention.

DESCRIPTION OF THE INVENTION

FIG. 1 illustrates apparatus that can be used to form and apply twomultipliers that are used in Reed-Solomon error control for certaindigital signals, such as the ECC phase of error control. Syndromecoefficients s0 and s1 are received by a multiplexer 25, whichselectively interleaves the s0 and s1 signals and passes the interleavedstream on one or more lines 27 to a Reed-Solomon multiplier module 29that also receives three known eight-bit multiplier coefficients, 8′hf4,8′hf5 and 8′hf7, from a lookup table or generator 31. The MUX 29 formseight-bit Reed-Solomon error control XOR sums:

c 0=8′hf4·s 0⊕8′hf7·s 1; and  (1)

c 1=8′hf5·s 0⊕8′hf7·s 1.  (2)

The MUX 29 issues the error control sums c0 and c1 on a line that isreceived and processed by a checkbyte error examination module 35 and isissued on an output line 37. The error control sums c0 and c1 are alsofed to a second group of (temp) registers 39 that feed these sums backto the MUX 29. Formation of the sums c0 and c1 requires use of manylogic gates and consumes several gate cycles in time, because of thesequential processing required.

The gate count and the cumulative processing time can be reduced in theformation of the product sums c0 and c1, according to the invention.FIG. 2 illustrates apparatus suitable for generating, storing and usingsyndrome components that are, in turn, used to form the checkbytecomponents used in Reed-Solomon error control, using an array ofeight-bit variables, x[7:0]={x[k]|k=0, 1, . . . ,7}={x[7],x[6],x[5],x[4],x[3],x[2],x[1],x[0]} and y[7:0]={y[k]|k=0, 1, .. . , 7}. The eight-bit variables x[7:0] involve powers α^(n) (n=0, 1, .. . , 7) of an eight-bit primitive α, that satisfies a selectedprimitive polynomial relation

p(α)=0.  (3)

For example, the primitive polynomial relation may be selected to be

p(α)=α⁸+α⁴+α³+α²+1=0,  (4)

in which event the “0” element, the “1” element and several powers of αbecome

0={0,0,0,0,0,0,0,0},

α⁰=α²⁵⁵={0,0,0,0,0,0,0,1}=1,

α={0,0,0,0,0,0,1,0},

α²={0,0,0,0,0,1,0,0},

α³={0,0,0,0,1,0,0,0},

α⁴={0,0,0,1,0,0,0,0},

α⁵={0,0,1,0,0,0,0,0},

α⁶={0,1,0,0,0,0,0,0},

α⁷={1,0,0,0,0,0,0,0},

α⁸={0,0,0,1,1,1,0,1}=α⁴+α³+α²+1,

α⁹={0,0,1,1,1,0,1,0}=α·α⁸=α⁵+α⁴+α³+α,

α²³⁰={1,1,1,1,0,1,0,0},

α²³¹={1,1,1,1,0,1,0,1},

α²³²={1,1,1,1,0,1,1,1},  (6)

where particular powers α^(n) (n=230, 231, 232) will be needed in thefollowing development. The remaining powers α^(n) (n=10≦n≦254) aregenerated using the particular primitive polynomial relation (4). Changeof the choice of primitive polynomial will cause a corresponding changein definition of most of the powers of α.

The following arrays of coefficients are formed, for example using theapparatus shown in FIG. 3, where x[k] is a scalar and y[7:0] is aneight-bit array.

x[0]·y[7:0]=z 0[7:0],  (6-0)

x[1]·y[7:0]α=z 1[7:0],  (6-1)

x[k]·y[7:0]α^(k) =zk[7:0] (k=0, 1, . . . , 7),  (6-k)

w 0[7:0]=z 0[7:0]+z 1[7:0],  (7-0)

w(k+1)[7:0]=zk[7:0]+wk[7:0] (k=0, 1, . . . , 5),  (7-k)

w 6[7:0]+c[7:0]=w 7[7:0],  (7-6)

where zk[7:0] also has eight entries, obtained by multiplying each ofthe eight entries in y[7:0] by the scalar x[k], and c[7:0] is a portionof a checkbyte c0 or c1. The variables x[7:0] and y[7:0] may be taken tobe any of the pairs {s0,8′hf4, {s0,8′hf5} and {s1,8′hf7} that appear inthe relations (1) and (2).

The checkbytes c0 and c1 are formed as follows. Two code word variabless0 and s1 are defined by $\begin{matrix}{{{s0} = {{\sum\limits_{n = 0}^{N}\quad {I\quad (n)\quad_{\quad}^{``}1_{\quad}^{''}}} = {{\left\{ {{I\quad (0)} + {I\quad (1)} + \ldots + {I\quad (N)}} \right\} \quad}^{``}1^{''}}}},} & (8) \\{{{s1} = {\sum\limits_{n = 0}^{N}\quad {I\quad (n)\quad \alpha^{n}}}},} & (9)\end{matrix}$

where, for example, the choices N=24 and N=43 correspond to P-paritycorrection and Q-parity correction, respectively, and I(n) is one of acolumn of data elements. Two 16-bit check bytes, c0=c0[15:8]+c0[7:0] andc1=c1[15:8]+c1[7:0], are added for every code word to detect up to twoerrors per code word and to allow correction of up to one error per codeword.

The check bytes c0 and c1 satisfy the error check relations

c 1+c 0+s 0=0,  (10)

c 1+c 0α+s 1α²=0.  (11)

One verifies from the relations (5), (10) and (11) that $\begin{matrix}{{\left( {1 + \alpha} \right) \cdot {c0}} = {{s0} + {\alpha^{2} \cdot {s1}}}} & (12) \\\begin{matrix}{{{c1} = \quad {{c0} + {s0}}},} \\{{c0} = \quad {\left( {1 + \alpha} \right)^{- 1}\left\{ {{s0} + {\alpha^{2} \cdot {s1}}} \right\}}} \\{= \quad {{\alpha^{- 25}\left\{ {{s0} + {\alpha^{2} \cdot {s1}}} \right\}} = {{\alpha^{255 - 25}\quad {s0}} + {\alpha^{257 - 25} \cdot {s1}}}}} \\{= \quad {{\alpha^{230} \cdot {s0}} + {\alpha^{232} \cdot {s1}}}}\end{matrix} & (13) \\\begin{matrix}{\quad {{= \quad {{8^{\prime}\quad {{hf4} \cdot {s0}}} + {8^{\prime}\quad {{hf7} \cdot {s1}}}}},}} \\{{c1} = \quad {{\alpha^{231} \cdot {s0}} + {\alpha^{232} \cdot {s1}}}}\end{matrix} & (14) \\{\quad {{= \quad {{8^{\prime}\quad {{hf5} \cdot {s0}}} + {8^{\prime}\quad {{hf7} \cdot {s1}}}}},}} & (15)\end{matrix}$

which exhibit the values of the (now-known) eight-bit coefficients8′hf4, 8′hf5 and 8′hf7. Higher order coefficients can be computed in asimilar manner. Where the arrays x and y have the forms

x=x ⁷α⁷ +x ⁶α⁶ +x ⁵α⁵ +x ⁴α⁴ +x ³α³ +x ²α² +x ¹α¹ +x ⁰α⁰,

y=y ⁷α⁷ +y ⁶α⁶ +y ⁵α⁵ +y ⁴α⁴ +y ³α³ +y ²α² +y ¹α¹ +y ⁰α⁰,

the product x*y of these arrays is defined as

x*y=x ⁷ yα ⁷ +x ⁶ yα ⁶ +x ⁵ yα ⁵ +x ⁴ yα ⁴ +x ³ yα ³ +x ² yα ² +x ¹ yα ¹+x ⁰ yα ⁰.  (16)

The coefficients 8′hf4, 8′hf5, 8′hf7 and others are part of an array ofcoefficients defined as follows.

8′hf5=8′hf4α,

8′hf7=8′hf5α,

8′hf3=8′hf7α,

8′hfb=8′hf3α,

8′heb=8′hfbα,

8′hcb=8′hebα,

8′h8b=8′hcbα,

8′h0b=8′h8bα,

8′h16=8′h0bα,

where additional higher terms in this array can also be defined, ifdesired, based on a Gray code expressed in hexadecimal format. Thequantities in (17) may be computed once and stored in software orhardware, and these quantities (and higher order coefficients) areconsidered known.

The input quantities s0 and s1 are characterized as sums of powers of α,as in (8) and (9). For example, the quantities 8′hf4·s0 and 8′hf5·s0 inthe relations (14) and (15) are the product of the coefficients 8′hf4and 8′hf5=8′hf4·α multiplied by a known numerical coefficient times aknown power of α and are easily computed once and stored, withoutrequiring recomputation of different (positive) powers of α.

Each of the quantities 8′hf4·s0, 8′hf5·s0 and 8′hf7·s1, if expressed ina conventional manner, will require use of approximately 3N−1 gates,including N−1 gates that form selected powers α^(m) (m=1, 2, . . . ,N−1), as illustrated in FIG. 3, and will require a substantial totaltime delay for the sequential operations indicated in FIG. 3. However,if the parity input quantity s1 is expressed as an (N+1)-tupleS1={s1[0], s1[1], s1[2], . . . , s1[N}}, the gate count can be reducedsubstantially (to N) by forming the usual logical product (AND) each ofa sequence of coefficient α^(k)·8′hf7 with each a sequence ofcoefficients s1[k] in the k-tuple S1.

FIG. 4 shows apparatus suitable for implementing, according to theinvention, formation of the Reed-Solomon products or multipliers used todefine c1 in (15), for the choice N=7. The number of gates required isreduced from 3N−1=23 in FIG. 3 to 2N−1=15 in FIG. 4. More generally, thecoefficients in (17) would include N+1 pre-computed input signals 8′hf4,α·8′hf4, α²·8′hf4, . . . , α^(N)·8′hf4, each directed to a separatetwo-input AND gate, with the input signals to the other terminal of eachAND gate being the scalar quantities s1[n] (n=0, 1, 2, . . . , N). Thecomputed quantities 8′hf4·α^(k) (k=0, 1, 2, . . . ) are preferablystored in a look-up table for subsequent use. Preferably, thecoefficients 8′hf7·α^(k) are provided in groups of N+1=8.

FIG. 5 shows apparatus suitable for implementing formation of theReed-Solomon multipliers used to define c0 in (14), where the inputsignals are the quantities 8′hf5·s0 (k=0, 1, 2, . . . ). Here, each ofthe input signals for the first terminal of the AND gates have the samevalue, such as 8′hf5.

Similarly, FIG. 6 shows apparatus suitable for implementing the inputsignals 8′hf5·s1. (k=0, 1, 2, . . . ).

The control bytes c0 and c1 are formed as indicated in (14) and (15) andare appended to the binary representation {I(0), I(1), . . . , I(N)} toimplement a Reed-Solomon error control procedure.

FIG. 7 is a flow chart illustrating one method of practicing theinvention. In step 71; acode word of length N+1 eight-bit arrays,expressible as a binary sequence {I_(n)} of bytes (n=0, 1, . . . , N),is provided. In step 73, an eight-bit primitive α satisfying a selectedprimitive polynomial relation p(α)=0, is provided. In step 75, aselected sequence of powers {J_(m)=α^(m)} of a is provided. In step 77,a first (N+1)-tuple code word element, s0, is computed as a logical sumof the eight-bit arrays I_(n) (n=0, 1, . . . , N). In step 79, a second(N+1)-tuple code word element, s1, is computed as a logical sum ofeight-bit product arrays I_(n)·J(n+N1) (n=0, 1, . . . , N). In step 81,the system provides a selected sequence {h(k)} (k=0, 1, . . . , N2−N1)of eight-bit arrays, with each element being proportional to a selectedpower of the primitive α. In step 83, a first control element, c0, isexpressed as a logical sum of products h(k+N1)·s0+h(k+N1+2)·s1 (k=0, 1,. . . , N2−N1). In step 85, a second control element, c1, is expressedas a logical sum of products h(k+N1)·s0+h(k+N1+2)·s1 (k=0, 1, . . . ,N2−N1). The quantities c0 and c1 may be interpreted as error controlcheckbytes for the code word sequence {I_(n)}. Optionally, in step 87,at least one of the error control checkbytes, c0 and c1, is appended tothe code word sequence {I_(n)}.

What is claimed is:
 1. A system for computing error control checkbytesfor a sequence of data, the system comprising a computer that isprogrammed: to receive a sequence of N+1 eight-bit data elements thatare to be processed for error control purposes, where N is a selectednon-negative integer; to compute a first error control syndrome s0 as asum of the sequence of data elements; to compute a second error controlsyndromes s1 as a sum of the sequence of data elements, each multipliedby a selected power of an eight-bit array α that satisfies a selectedprimitive polynomial relation p(α)=α⁸+α⁴+α³+α²+1=0; and to compute firstand second checkbytes, c0 and c1, for the sequence of data elements asfirst and second linear combinations c 0=s 0·α²³⁰ ⊕s 1·α²³², c 1=s0·α²³¹ ⊕s 1·α²³².
 2. The system of claim 1, wherein said computer isfurther programmed to analyze said checkbytes, c0 and c1, together withsaid data element sequence, to determine when said sequence contains atleast one data element error.
 3. The system of claim 1, wherein saidinteger N is selected to be
 24. 4. The system of claim 1, wherein saidinteger N is selected to be
 43. 5. A system of error control for adigital signal, the system comprising a computer that is programmed: toprovide a code word having a selected byte length N+1 and beingexpressible as an ordered sequence {I_(n)} (n=0, 1, . . . , N} of bytes,where I_(n)(=0 or 1) is a selected numerical coefficient; to provide aprimitive element α that satisfies a selected primitive polynomialequation p(α)=α⁸+α⁴+α³+α²+1=0; to provide a selected sequence ofeight-bit coefficients J(m)=α^(m) (N1≦m≦N2) that are powers of theprimitive α, where N1 and N2 are selected non-negative integerssatisfying N1=230 and N2=237; to compute a first (N+1)-tuple code wordelement, s0={s0[0], s0[1], . . . , s0[N]}, as a logical sum of thesequence of numerical values I_(n) (n=0, 1, . . . , N), all multipliedby an identity element 1; to compute a second (N+1)-tuple code wordelement, s1={s1[0], s1[1], . . . , s1[N}}, as a logical sum of theproducts I_(n)·J(n+N1); to store and provide a selected sequence ofelements h(k) (k=0, 1, . . . , N2−N1+2), with each element beingproportional to a selected power of the primitive element α; to computea first control element, c0, as a logical sum of productsh(k+N1)·s0+h(k+N1+2)·s1 (k=0, 1, . . . , N2−N1); to compute a secondcontrol element, c1, as a logical sum of productsh(k+N1+1)·s0+h(k+N1+2)·s1 (k=0, 1, . . . , N2−N1); and to interpret theelements c0 and c1 as error control checkbytes for the code word{I_(n)}.
 6. The system of claim 5, wherein said computer is furtherprogrammed to append at least one of said first and second checkbytes,c0 and c1, to said sequence {I_(n)}.
 7. The system of claim 5, whereinsaid integer N is selected to be
 24. 8. The system of claim 5, whereinsaid integer N is selected to be 43.